AC82G41SLGQ3 Datasheet, PDF (493/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
7
RO
6
RO
5
RO
4
RO
3
RO
Caching Mode (CM):
0 = Hardware does not cache not present and erroneous
entries in the context-cache and IOTLB. Invalidations
are not required for modifications to individual not
present or invalid entries. However, any modifications
that result in decreasing the effective permissions or
partial permission increases require invalidations for
0h
Core
them to be effective.
1 = Hardware may cache not present and erroneous
mappings in the context-cache or IOTLB. Any software
updates to the DMA-remapping structures (including
updates to not-present or erroneous entries) require
explicit invalidation.
Hardware implementations are recommended to support
operation corresponding to CM=0.
Protected High-Memory Region (PHMR):
0 = Protected high-memory region not supported.
1h
Core
1 = Protected high-memory region is supported.
DMA-remapping hardware implementations on Intel TXT
platforms supporting main memory above 4 GB are
required to support protected high-memory region.
Protected Low-Memory Region (PLMR):
0 = Protected low-memory region not supported.
1h
Core
1 = Protected low-memory region is supported.
DMA-remapping hardware implementations on Intel TXT
platforms are required to support protected low-memory
region.
Required Write-Buffer Flushing (RWBF):
0 = No write-buffer flushing needed to ensure changes to
memory-resident structures are visible to hardware.
1h
Core
1 = Software must explicitly flush the write buffers
(through the Global Command register) to ensure
updates made to memory-resident DMA-remapping
structures are visible to hardware.
Advanced Fault Logging (AFL):
0 = Advanced fault logging through memory-resident fault
0h
Core
log not supported. Only primary fault logging is
supported.
1 = Advanced fault logging is supported.
Datasheet
493