AC82G41SLGQ3 Datasheet, PDF (383/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.11 IDESBMSR—IDE Secondary Bus Master Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
Ah
00h
R/W, RO
8 bits
Reset: See bit definitions
This register implements the Bus Master Status register of the secondary channel.
Bit
Access
Default
Value
RST/PWR
Description
Simplex Only (SO): This bit indicates whether both Bus
Master Channels can be operated at the same time or not.
7
R/W
0b
Core
0 = Both can be operated independently
1 = Only one can be operated at a time.
Reset: Host system reset or D3->D0 transition.
Drive 1 DMA Capable (D1DC): This bit is read/write by
6
R/W
0b
Core
the host.
Reset: Host system Reset or D3->D0 transition of the
function.
Drive 0 DMA Capable (D0DC): This bit is read/write by
5
R/W
0b
Core
the host.
Reset: Host system Reset or D3->D0 transition of the
function.
4:3
RO
00b
Core
Reserved
Interrupt (INT): No functionality implemented. Read/
2
R/W
0b
Core
Write by Host.
Reset: Host System Reset or D3->D0 transition.
1
RO
0b
Core
Error (ER): Not implemented.
0
RO
0b
Core
Bus Master IDE Active (BMIA): Not implemented.
10.8.12 IDESBMDS1R—IDE Secondary Bus Master Device Specific
1 Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
Bh
00h
R/W
8 bits
Reset: ME system Reset.
This register implements the bus master Device Specific 1 register of the secondary
channel. This register is programmed by the Host for device specific data if any.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Device Specific Data1 (DSD1): Device Specific Data.
Datasheet
383