AC82G41SLGQ3 Datasheet, PDF (85/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5 DRAM Controller Registers
(D0:F0)
5.1
DRAM Controller Registers (D0:F0)
Warning:
Table 11.
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or
implemented in this component are simply not included in this document. The
reserved/unimplemented space in the PCI configuration header space is not
documented as such in this summary.
DRAM Controller Register Address Map (D0:F0) (Sheet 1 of 2)
Address
Offset
Register
Symbol
Register Name
Default Value
0–1h
2–3h
4–5h
6
8h
9–Bh
Dh
Eh
2C–2Ch
2E–2Fh
34h
40–47h
48–4Fh
52–53h
54–57h
60–67h
68–6Fh
90h
VID
DID
PCICMD
PCISTS
RID
CC
MLT
HDR
SVID
SID
CAPPTR
PXPEPBAR
MCHBAR
GGC
DEVEN
PCIEXBAR
DMIBAR
PAM0
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Master Latency Timer
Header Type
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
PCI Express Egress Port Base
Address
(G)MCH Memory Mapped Register
Range Base
GMCH Graphics Control Register
(82Q45, 82Q43, 82B43, 82G45,
82G43, 82G41 GMCH only)
Device Enable
PCI Express Register Range Base
Address
Root Complex Register Range
Base Address
Programmable Attribute Map 0
8086h
see register
description
0006h
0090h
see register
description
060000h
00h
00h
0000h
0000h
E0h
000000000000
0000h
000000000000
0000h
0030h
000023DBh
00000000E000
0000h
000000000000
0000h
00h
Access
RO
RO
RO, R/W
RO, R/WC
RO
RO
RO
RO
R/WO
R/WO
RO
RO, R/W/L
R/W/L, RO
R/W/L, RO
RO, R/W/L
RO, R/W/L,
R/W/L/K
RO, R/W/L
RO, R/W/L
Datasheet
85