AC82G41SLGQ3 Datasheet, PDF (118/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to ECBh.
Note:
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
15:4
3:0
Access
R/W/L
RO
Default
Value
001h
0000b
RST/
PWR
Core
Core
Description
Top of Low Usable DRAM (TOLUD): This register contains
bits 31:20 of an address one byte above the maximum DRAM
memory below 4 GB that is usable by the operating system.
Address bits 31:20 programmed to 01h implies a minimum
memory size of 1 MB. Configuration software must set this
value to the smaller of the following 2 choices: maximum
amount memory in the system minus ME stolen memory plus
one byte or the minimum address allocated for PCI memory.
Address bits 19:0 are assumed to be 0_0000h for the
purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming
address is less than the value programmed in this register.
Note that the Top of Low Usable DRAM is the lowest address
above both Graphics Stolen memory and TSEG. BIOS
determines the base of Graphics Stolen Memory by
subtracting the Graphics Stolen Memory Size from TOLUD
and further decrements by TSEG size to determine base of
TSEG. This register must be 64 MB aligned when reclaim is
enabled.
Reserved
5.1.36
ERRSTS—Error Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
C8-C9h
0000h
RO, R/WC/S
16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a 1 to it.
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Datasheet