AC82G41SLGQ3 Datasheet, PDF (228/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Direct Memory Interface Registers (DMIBAR)
7.12
DMILCTL—DMI Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
88-89h
0000h
RO, R/W
16 bits
This register allows control of DMI.
Bit
15:2
7
6:2
1:0
7.13
Access
RO
R/W
RO
R/W
Default
Value
00h
0b
0h
00b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Reserved
Reserved
Active State Power Management Support (ASPMS):
This register controls the level of active state power
management supported on the given link.
00 = Disabled
01 = Reserved
10 = L1 Entry Enabled
11 = L1 Entry Enabled
DMILSTS—DMI Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
8A-8Bh
0001h
RO
16 bits
This register indicates DMI status.
Bit
15:10
Access
RO
9:4
RO
3:0
RO
Default
Value
00h
00h
1h
RST/PWR
Description
Core
Core
Core
Reserved
Negotiated Width (NWID): This register indicates
negotiated link width. This field is valid only when the link
is in the L0 or L1 states (after link width negotiation is
successfully completed).
00h = Reserved
01h = X1
02h = X2
04h = X4
All other encodings are reserved.
Negotiated Speed (NSPD): This field indicates
negotiated link speed.
1h = 2.5 Gb/s
All other encodings are reserved.
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Datasheet