AC82G41SLGQ3 Datasheet, PDF (173/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6 Host-PCI Express* Registers
(D1:F0)
Warning:
Note:
Table 13.
Device 1 contains the controls associated with the PCI Express x16 root port that is the
intended to attach as the point for external graphics. It is typically referred to as PCI
EXPRESS-G (PCI Express graphics) port. In addition, it also functions as the virtual PCI-
to-PCI bridge.
When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits.
Reserved and Preserved:
1. Reserved for future R/W implementations; software must preserve value read for
writes to bits.
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first Disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
PCI Express* Register Address Map (D1:F0)
Address
Offset
0–1h
Register
Symbol
VID1
Register Name
Vendor Identification
2–3h
DID1
Device Identification
4–5h
6–7h
PCICMD1
PCISTS1
PCI Command
PCI Status
8h
RID1
Revision Identification
9–Bh
Ch
Eh
18h
19h
1Ah
1Ch
1Dh
1E–1Fh
20–21h
CC1
CL1
HDR1
PBUSN1
SBUSN1
SUBUSN1
IOBASE1
IOLIMIT1
SSTS1
MBASE1
Class Code
Cache Line Size
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
Default
Value
8086h
see register
description
0000h
0010h
see register
description
060400h
00h
01h
00h
00h
00h
F0h
00h
0000h
FFF0h
Access
RO
RO
RO, R/W
RO, R/WC
RO
RO
R/W
RO
RO
R/W
R/W
RO, R/W
R/W, RO
R/WC, RO
R/W, RO
Datasheet
173