AC82G41SLGQ3 Datasheet, PDF (320/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.1.9
BIST— Built In Self Test
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
Fh
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7
RO
0b
Core
BIST Capable (BC): Not implemented, hardwired to 0.
6:0
RO
0000000b
Core
Reserved
10.1.10 HECI_MBAR— HECI MMIO Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
10-17h
0000000000000004h
RO, R/W
64 bits
This register allocates space for the HECI memory mapped registers.
Bit
63:4
3
2:1
0
Access
R/W
RO
RO
RO
Default
Value
000000000
000000h
0b
10b
0b
RST/PWR
Description
Core
Core
Core
Core
Base Address (BA): Base address of register memory
space.
Prefetchable (PF): This bit indicates that this range is not
pre-fetchable
Type (TP): This field indicates that this range can be
mapped anywhere in 64-bit address space. Note that the
(G)MCH only uses bits 35:4 of the base address field as the
(G)MCH only decodes FSB address bits 35:4.
Resource Type Indicator (RTE): Indicates a request for
register memory space.
320
Datasheet