AC82G41SLGQ3 Datasheet, PDF (390/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.7
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
Dh
00h
RO
8 bits
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Master Latency Timer (MLT): Not implemented since
the function is in MCH.
10.9.8
HTYPE—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
Eh
< Not Defined >
< Not Defined >
8 bits
Register is Not implemented. Reads return 0.
10.9.9
BIST—Built In Self Test
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
Fh
Not Defined
Not Defined
8 bits
This optional register is not implemented.
390
Datasheet