AC82G41SLGQ3 Datasheet, PDF (90/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
8
7
6
5
4
3:0
5.1.5
Access
Default
Value
R/WC
0b
RO
1b
RO
0b
RO
0b
RO
1b
RO
0000b
RST/
PWR
Core
Core
Core
Core
Core
Core
Description
Master Data Parity Error Detected (DPD): This bit is
set when DMI received a Poisoned completion from the
ICH.
This bit can only be set when the Parity Error Enable bit in
the PCI Command register is set.
Fast Back-to-Back (FB2B): This bit is hardwired to 1.
Writes to these bit positions have no effect. Device 0 does
not physically connect to PCI_A. This bit is set to 1
(indicating fast back-to-back capability) so that the
optimum setting for PCI_A is not limited by the (G)MCH.
Reserved
66 MHz Capable: Does not apply to PCI Express. Must be
hardwired to 0.
Capability List (CLIST): This bit is hardwired to 1 to
indicate to the configuration software that this device/
function implements a list of new capabilities. A list of new
capabilities is accessed via register CAPPTR at
configuration address offset 34h. Register CAPPTR
contains an offset pointing to the start address within
configuration space of this device where the Capability
Identification register resides.
Reserved
RID—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
8h
See description below
RO
8 bits
This register contains the revision number of the (G)MCH Device 0. These bits are read
only and writes to this register have no effect.
Bit
Access
Default
RST/
Value
PWR
Description
Revision Identification Number (RID): This is an 8-bit
7:0
RO
See
description
Core
value that indicates the revision identification number for
the (G)MCH Device 0. Refer to the Intel^® 4 Series Chipset
Family Specification Update for the value of this register.
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Datasheet