AC82G41SLGQ3 Datasheet, PDF (256/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.38
LCAP—Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
AC–AFh
03214D02h
RO, RWO
32 bits
This register indicates PCI Express device specific capabilities.
Bit
31:24
23:22
21
20
19
18
17:15
Access
RO
RO
RO
RO
RO
RO
RWO
Default
Value
03h
000b
1b
0b
0b
0b
010b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Description
Port Number (PN): This field indicates the PCI Express port number
for the given PCI Express link. Matches the value in Element Self
Description[31:24].
Reserved
Link Bandwidth Notification Capability: A value of 1b indicates
support for the Link Bandwidth Notification status and interrupt
mechanisms. This capability is required for all Root Ports and Switch
downstream ports supporting Links wider than x1 and/or multiple
Link speeds.
This field is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification
capability must hardwire this bit to 0b.
Data Link Layer Link Active Reporting Capable (DLLLARC): For
a Downstream Port, this bit must be set to 1b if the component
supports the optional capability of reporting the DL_Active state of
the Data Link Control and Management State Machine.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
Surprise Down Error Reporting Capable (SDERC): For a
Downstream Port, this bit must be set to 1b if the component
supports the optional capability of detecting and reporting a Surprise
Down error condition.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
Clock Power Management (CPM): A value of 1b in this bit
indicates that the component tolerates the removal of any reference
clock(s) when the link is in the L1 and L2/3 Ready link states. A value
of 0b indicates the component does not have this capability and that
reference clock(s) must not be removed in these link states.
This capability is applicable only in form factors that support "clock
request" (CLKREQ#) capability.
For a multi-function device, each function indicates its capability
independently. Power Management configuration software must only
permit reference clock removal if all functions of the multifunction
device indicate a 1b in this bit.
L1 Exit Latency (L1ELAT): Indicates the length of time this Port
requires to complete the transition from L1 to L0. The value 010 b
indicates the range of 2 us to less than 4 us.
Both bytes of this register that contain a portion of this field must be
written simultaneously in order to prevent an intermediate (and
undesired) value from ever existing.
256
Datasheet