AC82G41SLGQ3 Datasheet, PDF (127/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
15:10
9:0
Programming Guide
Non-stacked mode
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in ch0 rank0 (in 64 MB increments)
C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64 MB increments)
and so on.
If Channel 1 is empty, all of the C1DRBs are programmed with 00h.
C1DRB0 = Total memory in ch1 rank0 (in 64 MB increments)
C1DRB1 = Total memory in ch1 rank0 + ch1 rank1 (in 64 MB increments)
and so on.
Stacked mode:
CODRBs:
Similar to Non-stacked mode.
C1DRB0, C1DRB1 and C1DRB2:
They are also programmed similar to non-stacked mode. Only exception is, the DRBs
corresponding to the topmost populated rank and the (unpopulated) higher ranks in
Channel 1 must be programmed with the value of the total Channel 1 population plus
the value of total Channel 0 population (C0DRB3).
Example: If only ranks 0 and 1 are populated in Ch1 in stacked mode, then
C1DRB0 = Total memory in ch1 rank0 (in 64 MB increments)
C1DRB1 = C0DRB3 + Total memory in ch1 rank0 + ch1 rank1 (in 64 MB increments)
(rank 1 is the topmost populated rank)
C1DRB2 = C1DRB1
C1DRB3 = C1DRB1
C1DRB3:
C1DRB3 = C0DRB3 + Total memory in Channel 1.
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 0 Dram Rank Boundary Address 0
(C0DRBA0): This register defines the DRAM rank
boundary for rank0 of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
This register is locked by ME stolen Memory lock.
Datasheet
127