AC82G41SLGQ3 Datasheet, PDF (526/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
Table 29.
13.1.5
Host Interface 4X, 2X, and 1X Signal Groups
Signals
Associated Clock or Strobe
FSB_ADSB, FSB_BNRB, FSB_BPRIB,
FSB_DEFERB, FSB_DBSYB, FSB_DRDYB,
FSB_HITB, FSB_HITMB, FSB_LOCKB,
FSB_RSB_[2:0], FSB_TRDYB, RSTINB
FSB_AB_[16:3], FSB_REQB_[4:0]
FSB_AB_[35:17]
FSB_DB_[15:0], FSB_DINVB_0
FSB_DB_[31:16], FSB_DINVB_1
FSB_DB_[47:32], FSB_DINVB_2
FSB_DB_[63:48], FSB_DINVB_3
HPL_CLKINP
HPL_CLKINN
FSB_ADSTBB_0
FSB_ADSTBB_1
FSB_DSTBPB_0, FSB_DSTBNB_0
FSB_DSTBPB_1, FSB_DSTBNB_1
FSB_DSTBPB_2, FSB_DSTBNB_2
FSB_DSTBPB_3, FSB_DSTBNB_3
Signal
Group
1X
2X
4X
APIC Cluster Mode Support
APIC Cluster mode support is required for backwards compatibility with existing
software, including various operating systems.
The (G)MCH supports three types of interrupt re-direction:
• Physical
• Flat-Logical
• Clustered-Logical
If more than one xTPR register set in the arbitration pool has the same lowest value, or
if all enabled xTPR Task Priority fields are 1111b, the xTPR register set referenced by
the lowest value TPR_SEL[3:0] is the “winner”.
The “winning” xTPR register set provides the values to be substituted in the
Aa[19:12]# and Aa[7:4]# fields of the FSB Interrupt Message Transaction driven by
the (G)MCH.
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Datasheet