AC82G41SLGQ3 Datasheet, PDF (416/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.8
TXT.DID—TXT Device ID Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
110-117h
8003h
RW, RO
64 bits
Contains the TXT ID for the MCH or root chipset component. This register is Sticky.
Bit
63:48
47:32
31:16
15:0
Access
Default
Value
Description
RW
0000h
TXT ID Extensions (TXT.ID.EXT): This field is Read/Write. The default
value for this register is 0. This is an extension onto the other ID fields.
RO
00000000000
01111b
Revision ID (TXT.RID):
RO
8003h
Device ID (TXT.DID): 8003h for Intel 4 Series Chipset 82Q45 and 82Q43.
RO
8086h
Vendor ID (TXT.VID): This register field contains the PCI standard
identification for Intel, 8086h.
11.1.9
TXT.CMD.FLUSH-WB—TXT Flush Write Buffer Command
This command flushes the chipset write buffers. The MLE writes to this register as part
of the MPT update sequence.
11.1.10 TXT.SINIT.MEMORY.BASE—TXT SINIT Code Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
270-277h
0000000000000000h
RW, RO
64 bits
This register contains the physical base address of the memory region set aside by the
BIOS for loading an SINIT AC module. The system software reads this register to locate
the SINIT module (which may have been loaded by the BIOS) or to find a location to
load the SINIT module.
Bit Access
63:36
RO
35:12
RW
11:0
RO
Default
Value
Description
0000000h
000000h
000h
Reserved
SINIT Code Base (TXT.SINIT.MEMORY.BASE): Base address of the
SINIT code. Hardware does not use the information contained in this register.
It is used as a mailbox between two pieces of software.
NOTE: Bits 11:0 are not implemented because the SINIT code must be
aligned to a 4K page boundary.
Systems supporting a 36 bit address space may make bits 63:36 as RO with
reads returning '0'.
Reserved
416
Datasheet