AC82G41SLGQ3 Datasheet, PDF (133/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
12:9
8:0
Access
R/W
R/W
Default
Value
RST/PWR
Description
0h
000000000b
Core
Core
ALLPRE to ACT Delay (C0sd0_cr_preall_act): From
the launch of a prechargeall command wait for these many
# of memory clocks before launching a activate command.
This field corresponds to tPALL_RP. in the DDR
Specification.
REF to ACT Delayed (C0sd_cr_rfsh_act): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between REF and ACT
commands to the same rank. This field corresponds to
tRFC in the DDR Specification.
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
256-257h
0000h
R/W
16 bits
Bit
Access
15:12
R/W
11:8
R/W
7:4
R/W
3:0
R/W
Default
Value
0h
0h
0h
0h
RST/PWR
Description
Core
Core
Core
Core
ACT To Write Delay (C0sd_cr_act_wr): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and WRITE
commands to the same rank-bank. This field corresponds
to tRCD_wr in the DDR Specification.
Same Rank Write To Write Delayed
(C0sd_cr_wrsr_wr): This configuration register
indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to the same rank.
Different Rank Write to Write Delay
(C0sd_cr_wrdr_wr): This configuration register
indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to different ranks. This
field corresponds to tWR_WR in the DDR Specification.
READ To WRTE Delay (C0sd_cr_rd_wr): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and WRITE
commands. This field corresponds to tRD_WR in the DDR
Specification.
Datasheet
133