AC82G41SLGQ3 Datasheet, PDF (411/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.1
TXT.STS—TXT Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/TXT Specific
0-2h
000010h
RO
24 bits
00h
This register is used to read the status of the TXT Command/Status Engine functional
block in the chipset.
Bit Access
23:17
RO
16
RO
15
RO
14:8
RO
7
RO
6:5
RO
4:4
RO
3:2
RO
1
RO
0
RO
Default
Value
Description
0h
Reserved
TXT.LOCALITY2.OPEN.STS (TXT.LOCALITY2.OPEN.STS): This bit is set
when either the TXT.CMD.OPEN.LOCALITY2 command or the
0b
TXT.CMD.OPEN.PRIVATE is seen by the chipset. It is cleared on reset or when
either TXT.CMD.CLOSE.LOCALITY2 or TXT.CMD.CLOSE.PRIVATE is seen. This bit
can be used by SW as a positive indication that the command has taken effect.
TXT.LOCALITY1.OPEN.STS (TXT.LOCALITY1.OPEN.STS):
This bit is set when the TXT.CMD.OPEN.LOCALITY1 command is seen by the
0b
chipset. It is cleared on reset or when TXT.CMD.CLOSE.LOCALITY1 is seen. This
bit can be used by SW as a positive indication that the command has taken
effect.
0b
Reserved
TXT Private-Open Status (TXT.PRIVATE-OPEN.STS): This bit will be set to
0b
1 when the TXT Private address is opened. This bit cleared by the
TXT.CMD.CLOSE-PRIVATE or by a system reset.
0b
Reserved
1b
Reserved
0b
Reserved
SEXIT Done Status (SEXIT.DONE.STS): This bit is set when all of the bits in
the TXT.THREADS.JOIN register are clear 0. Thus, this bit will be set
0b
immediately after reset (since the bits are all 0). This bit will be cleared on the
receipt of the first TXT.CYC.SENTER-ACK. Once all threads have done the
TXT.CYC.SEXIT-ACK, the TXT.THREAD.JOIN register will be 0, so the chipset will
set this bit.
SENTER Done Status (SENTER.DONE.STS): The chipset sets this bit when it
sees all of the threads have done the TXT.CYC.SENTER-ACK. When any of the
0b
threads does the TXT.CYC.SEXIT-ACK, the TXT.THREADS.JOIN and
TXT.THREADS.EXISTS registers will not be equal, so the chipset will clear this
bit.
Datasheet
411