AC82G41SLGQ3 Datasheet, PDF (517/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
5:0
WO
Address Mask (AM): The value in this field specifies the
number of low-order bits of the ADDR field that must be
masked for the invalidation operation. Mask field enables
software to request invalidation of contiguous mappings for
size-aligned regions. For example: Mask Value ADDR bits
masked Pages invalidated
0 None 1
0s
Core
1 12 2
2 13 : 12 4
3 14 : 12 8
4 15 : 12 16
...... ....... .......
Hardware implementations report the maximum supported
mask value through the Capability register.
Value returned on read of this field is undefined.
Datasheet
517