AC82G41SLGQ3 Datasheet, PDF (134/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.11
C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
258-25Ah
000000h
R/W, RO
24 bits
Bit
23:21
Access
RO
20:17
R/W
16:12
R/W
11:8
R/W
7:4
R/W
3:0
R/W
Default
Value
000b
0h
00000b
0000b
0000b
0000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Reserved
Min ACT To READ Delayed (C0sd_cr_act_rd): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field corresponds
to tRCD_rd in the DDR Specification.
Same Rank Write To READ Delayed
(C0sd_cr_wrsr_rd): This configuration register indicates
the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to the same rank. This
field corresponds to tWTR in the DDR Specification.
Different Ranks Write To READ Delayed
(C0sd_cr_wrdr_rd): This configuration register indicates
the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks. This
field corresponds to tWR_RD in the DDR Specification.
Same Rank Read To Read Delayed
(C0sd_cr_rdsr_rd): This configuration register indicates
the minimum allowed spacing (in DRAM clocks) between
two READ commands to the same rank.
Different Ranks Read To Read Delayed
(C0sd_cr_rddr_rd): This configuration register indicates
the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field
corresponds to tRD_RD in the DDR Specification.
134
Datasheet