AC82G41SLGQ3 Datasheet, PDF (155/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.39
EPDCKECONFIGREG—EPD CKE Related Configuration
Registers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR
A28-A2Ch
00E0000000h
R/W
40 bits
0h
Bit
39:35
34:32
31:29
28:27
26:24
23:20
19:17
16:15
14
13
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
Default
Value
00000b
000b
111b
00b
000b
0h
000b
0h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
EPDunit TXPDLL Count (EPDTXPDLL): This field specifies
the delay from precharge power down exit to a command
that requires the DRAM DLL to be operational. The commands
are read/write.
EPDunit TXP count (EPDCKETXP): This field specifies the
timing requirement for Active power down exit or fast exit
pre-charge power down exit to any command or slow exit
pre-charge power down to Non-DLL (rd/wr/odt). command.
Mode Select (sd0_cr_sms): Mode Select register: This
field setting indicates the mode in which the controller is
operating in.
111 = Indicates normal mode of operation, else special
mode of operation.
EPDunit EMRS command select. (EPDEMRSSEL): EMRS
mode to select BANK address.
01 = EMRS
10 = EMRS2
11 = EMRS3
CKE pulse width requirement in high phase
(sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse
width requirement in high phase.
one-hot active rank population (ep_scr_actrank): This
field indicates the active rank in a one hot manner.
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse
width requirement in low phase.
Reserved
EPDunit MPR mode (EPDMPR):
1 = MPR mode
0 = Normal mode
In MPR mode, only read cycles must be issued by Firmware.
Page Results are ignored by DCS and just issues the read chip
select.
EPDunit Power Down enable for ODT Rank
(EPDOAPDEN): This bit enables the ODT ranks to
dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
Datasheet
155