AC82G41SLGQ3 Datasheet, PDF (15/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

12.3.2 CAP_REG—Capability Register................................................................ 490
12.3.3 ECAP_REG—Extended Capability Register ................................................ 495
12.3.4 GCMD_REG—Global Command Register................................................... 497
12.3.5 GSTS_REG—Global Status Register......................................................... 502
12.3.6 RTADDR_REG—Root-Entry Table Address Register .................................... 503
12.3.7 CCMD_REG—Context Command Register................................................. 504
12.3.8 FSTS_REG—Fault Status Register ........................................................... 506
12.3.9 FECTL_REG—Fault Event Control Register................................................ 508
12.3.10FEDATA_REG—Fault Event Data Register ................................................. 509
12.3.11FEADDR_REG—Fault Event Address Register ............................................ 509
12.3.12FEUADDR_REG—Fault Event Upper Address Register................................. 510
12.3.13AFLOG_REG—Advanced Fault Log Register .............................................. 510
12.3.14PMEN_REG—Protected Memory Enable Register........................................ 511
12.3.15PLMBASE_REG—Protected Low Memory Base Register............................... 512
12.3.16PLMLIMIT_REG—Protected Low Memory Limit Register .............................. 513
12.3.17PHMBASE_REG—Protected High Memory Base Register ............................. 514
12.3.18PHMLIMIT_REG—Protected High Memory Limit Register............................. 515
12.3.19IVA_REG—Invalidate Address Register .................................................... 516
12.3.20IOTLB_REG—IOTLB Invalidate Register ................................................... 518
12.3.21FRCD_REG—Fault Recording Registers .................................................... 522
13 Functional Description ........................................................................................... 525
13.1 Host Interface................................................................................................. 525
13.1.1 FSB IOQ Depth .................................................................................... 525
13.1.2 FSB OOQ Depth ................................................................................... 525
13.1.3 FSB GTL+ Termination .......................................................................... 525
13.1.4 FSB Dynamic Bus Inversion ................................................................... 525
13.1.5 APIC Cluster Mode Support.................................................................... 526
13.2 System Memory Controller ............................................................................... 527
13.2.1 System Memory Organization Modes....................................................... 527
13.2.1.1 Single Channel Mode ............................................................... 527
13.2.1.2 Dual Channel Modes................................................................ 527
13.2.2 System Memory Technology Supported ................................................... 529
13.3 PCI Express* .................................................................................................. 530
13.3.1 PCI Express* Architecture ..................................................................... 530
13.3.1.1 Transaction Layer ................................................................... 530
13.3.1.2 Data Link Layer ...................................................................... 530
13.3.1.3 Physical Layer ........................................................................ 530
13.3.2 PCI Express* on (G)MCH ....................................................................... 530
13.4 Integrated Graphics Device
(Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43 GMCH Only) .................................. 532
13.4.1 3D and Video Engines for Graphics Processing.......................................... 532
13.4.1.1 3D Engine Execution Units (EUs)............................................... 533
13.4.1.2 3D Pipeline ............................................................................ 533
13.4.2 Video Engine ....................................................................................... 534
13.4.3 2D Engine ........................................................................................... 534
13.4.3.1 Chipset VGA Registers ............................................................. 534
13.4.3.2 Logical 128-Bit Fixed BLT and 256 Fill Engine ............................. 534
13.5 Display Interfaces
(Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 GMCH Only) ....................... 535
13.5.1 Analog Display Port Characteristics ......................................................... 535
13.5.1.1 Integrated RAMDAC ................................................................ 536
13.5.1.2 Sync Signals .......................................................................... 536
13.5.1.3 VESA/VGA Mode ..................................................................... 536
13.5.1.4 DDC (Display Data Channel)..................................................... 536
13.5.2 Digital Display Interface ........................................................................ 536
Datasheet
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