AC82G41SLGQ3 Datasheet, PDF (441/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
33:32
W
31:16
W
15:0
R/W
Default
Value
0h
0000h
0000h
RST/PWR
Description
Core
Core
Core
Function Mask (FM): This field specifies which bits of the
function number portion (least significant three bits) of the
SID field to mask when performing device-selective
invalidations.
00 =No bits in the SID field masked.
01 =Mask most significant bit of function number in the
SID field.
10 =Mask two most significant bit of function number in
the SID field.
11 =Mask all three bits of function number in the SID
field.
The device(s) specified through the FM and SID fields
must correspond to the domain-ID specified in the DID
field.
Value returned on read of this field is undefined.
Source ID (SID): This field indicates the source-ID of the
device whose corresponding context-entry needs to be
selectively invalidated. This field along with the FM field
must be programmed by software for device-selective
invalidation requests.
Value returned on read of this field is undefined.
Domain-ID (DID): This field indicates the ID of the
domain whose context-entries needs to be selectively
invalidated. This field must be programmed by software
for both domain-selective and device-selective invalidation
requests.
The Capability register reports the domain-ID width
supported by hardware. Software must ensure that the
value written to this field is within this limit.
Hardware may ignore and not implement bits 15:N where
N is the supported domain-ID width reported in the
capability register.
Datasheet
441