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AC82G41SLGQ3 Datasheet, PDF (6/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family | |||
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5.2.23 C1CYCTRKWRâChannel 1 CYCTRK WR .................................................... 144
5.2.24 C1CYCTRKRDâChannel 1 CYCTRK READ .................................................. 145
5.2.25 C1CKECTRLâChannel 1 CKE Control ....................................................... 145
5.2.26 C1REFRCTRLâChannel 1 DRAM Refresh Control........................................ 147
5.2.27 C1ODTCTRLâChannel 1 ODT Control....................................................... 149
5.2.28 EPC0DRB0âEP Channel 0 DRAM Rank Boundary Address 0 ........................ 149
5.2.29 EPC0DRB1âEP Channel 0 DRAM Rank Boundary Address 1 ........................ 150
5.2.30 EPC0DRB2âEP Channel 0 DRAM Rank Boundary Address 2 ........................ 150
5.2.31 EPC0DRB3âEP Channel 0 DRAM Rank Boundary Address 3 ........................ 150
5.2.32 EPC0DRA01âEP Channel 0 DRAM Rank 0,1 Attribute................................. 151
5.2.33 EPC0DRA23âEP Channel 0 DRAM Rank 2,3 Attribute................................. 151
5.2.34 EPDCYCTRKWRTPREâEPD CYCTRK WRT PRE ............................................ 152
5.2.35 EPDCYCTRKWRTACTâEPD CYCTRK WRT ACT ........................................... 152
5.2.36 EPDCYCTRKWRTWRâEPD CYCTRK WRT WR ............................................. 153
5.2.37 EPDCYCTRKWRTREFâEPD CYCTRK WRT REF ............................................ 153
5.2.38 EPDCYCTRKWRTRDâEPD CYCTRK WRT READ........................................... 154
5.2.39 EPDCKECONFIGREGâEPD CKE Related Configuration Registers................... 155
5.2.40 EPDREFCONFIGâEP DRAM Refresh Configuration...................................... 156
5.2.41 TSC1âThermal Sensor Control 1 ............................................................ 158
5.2.42 TSC2âThermal Sensor Control 2 ............................................................ 159
5.2.43 TSSâThermal Sensor Status .................................................................. 161
5.2.44 TSTTPâThermal Sensor Temperature Trip Point........................................ 162
5.2.45 TCOâThermal Calibration Offset ............................................................. 163
5.2.46 THERM1âHardware Throttle Control ....................................................... 164
5.2.47 TISâThermal Interrupt Status................................................................ 165
5.2.48 TSMICMDâThermal SMI Command ......................................................... 167
5.2.49 PMSTSâPower Management Status......................................................... 168
5.3 EPBAR............................................................................................................ 169
5.3.1 EPESDâEP Element Self Description........................................................ 169
5.3.2 EPLE1DâEP Link Entry 1 Description ....................................................... 170
5.3.3 EPLE1AâEP Link Entry 1 Address............................................................ 170
5.3.4 EPLE2DâEP Link Entry 2 Description ....................................................... 171
5.3.5 EPLE2AâEP Link Entry 2 Address............................................................ 172
6 Host-PCI Express* Registers (D1:F0)..................................................................... 173
6.1 Host-PCI Express* Register Description (D1:F0) .................................................. 175
6.1.1 VID1âVendor Identification ................................................................... 175
6.1.2 DID1âDevice Identification.................................................................... 175
6.1.3 PCICMD1âPCI Command ...................................................................... 176
6.1.4 PCISTS1âPCI Status............................................................................. 178
6.1.5 RID1âRevision Identification ................................................................. 179
6.1.6 CC1âClass Code .................................................................................. 180
6.1.7 CL1âCache Line Size ............................................................................ 180
6.1.8 HDR1âHeader Type.............................................................................. 181
6.1.9 PBUSN1âPrimary Bus Number ............................................................... 181
6.1.10 SBUSN1âSecondary Bus Number ........................................................... 181
6.1.11 SUBUSN1âSubordinate Bus Number ....................................................... 182
6.1.12 IOBASE1âI/O Base Address .................................................................. 182
6.1.13 IOLIMIT1âI/O Limit Address .................................................................. 183
6.1.14 SSTS1âSecondary Status...................................................................... 183
6.1.15 MBASE1âMemory Base Address ............................................................. 184
6.1.16 MLIMIT1âMemory Limit Address ............................................................ 185
6.1.17 PMBASE1âPrefetchable Memory Base Address ......................................... 186
6.1.18 PMLIMIT1âPrefetchable Memory Limit Address......................................... 187
6.1.19 PMBASEU1âPrefetchable Memory Base Address Upper .............................. 188
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Datasheet
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