SH7706 Datasheet, PDF (90/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Table 2.10 lists the system control instructions.
Table 2.10 System Control Instructions
Instruction
Operation
CLRMAC
0 → MACH, MACL
CLRS
0→S
CLRT
0→T
LDC Rm,SR
Rm → SR
LDC Rm,GBR
Rm → GBR
LDC Rm,VBR
Rm → VBR
LDC Rm,SSR
Rm → SSR
LDC Rm,SPC
Rm → SPC
LDC Rm,R0_BANK Rm → R0_BANK
LDC Rm,R1_BANK Rm → R1_BANK
LDC Rm,R2_BANK Rm → R2_BANK
LDC Rm,R3_BANK Rm → R3_BANK
LDC Rm,R4_BANK Rm → R4_BANK
LDC Rm,R5_BANK Rm → R5_BANK
LDC Rm,R6_BANK Rm → R6_BANK
LDC Rm,R7_BANK Rm → R7_BANK
LDC.L @Rm+,SR
(Rm) → SR, Rm + 4 → Rm
LDC.L @Rm+,GBR
(Rm) → GBR, Rm + 4 → Rm
LDC.L @Rm+,VBR
(Rm) → VBR, Rm + 4 → Rm
LDC.L @Rm+,SSR
(Rm) → SSR, Rm + 4 → Rm
LDC.L @Rm+,SPC
(Rm) → SPC, Rm + 4 → Rm
LDC.L @Rm+,
R0_BANK
(Rm) → R0_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R1_BANK
(Rm) → R1_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R2_BANK
(Rm) → R2_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R3_BANK
(Rm) → R3_BANK,
Rm + 4 → Rm
Code
0000000000101000
0000000001001000
0000000000001000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111110
0100mmmm01001110
0100mmmm10001110
0100mmmm10011110
0100mmmm10101110
0100mmmm10111110
0100mmmm11001110
0100mmmm11011110
0100mmmm11101110
0100mmmm11111110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00110111
0100mmmm01000111
0100mmmm10000111
Privileged
Mode
Cycles T Bit
—
1
—
—
1
—
—
1
0
√
5
LSB
—
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
3
—
√
7
LSB
—
5
—
√
5
—
√
5
—
√
5
—
√
5
—
0100mmmm10010111 √
5
—
0100mmmm10100111 √
5
—
0100mmmm10110111 √
5
—
Rev. 5.00 May 29, 2006 page 42 of 698
REJ09B0146-0500