SH7706 Datasheet, PDF (223/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
10 A0BST1 0
R/W Area 0 Burst ROM Control
9 A0BST0 0
R/W Specify whether to use burst ROM in physical space
area 0. When burst ROM is used, set the number of
burst transfers.
00: Access area 0 as ordinary memory
01: Access area 0 as burst ROM (4 consecutive
accesses). Can be used when bus width is 8, 16,
or 32.
10: Access area 0 as burst ROM (8 consecutive
accesses). Can be used when bus width is 8 or
16.
01: Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
8 A5BST1 0
7 A5BST0 0
R/W Area 5 Burst Enable
R/W Specify whether to use burst ROM and PCMCIA burst
mode in physical space area 5. When burst ROM and
PCMCIA burst mode are used, set the number of burst
transfers.
00: Access area 5 as ordinary memory
01: Burst access of area 5 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
10: Burst access of area 5 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
11: Burst access of area 5 (16 consecutive accesses).
Can be used only when bus width is 8.
6 A6BST1 0
5 A6BST0 0
R/W Area 6 Burst Enable
R/W Specify whether to use burst ROM and PCMCIA burst
mode in physical space area 6. When burst ROM and
PCMCIA burst mode are used, set the number of burst
transfers.
00: Access area 6 as ordinary memory
01: Burst access of area 6 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
10: Burst access of area 6 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
11: Burst access of area 6 (16 consecutive accesses).
Can be used only when bus width is 8.
Rev. 5.00 May 29, 2006 page 175 of 698
REJ09B0146-0500