SH7706 Datasheet, PDF (313/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. The dual address mode has direct address transfer mode and indirect
address transfer mode. In the bus mode, the burst mode or the cycle steal mode can be selected.
9.4.1 DMA Transfer Flow
After the DMA source address registers (SAR_0 to SAR_3), DMA destination address registers
(DAR_0 to DAR_3), DMA transfer count registers (DMATCR_0 to DMATCR_3), DMA channel
control registers (CHCR_0 to CHCR_3), and DMA operation register (DMAOR) are set, the
DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of
data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
4. When an NMI interrupt is generated or an address error occurs during DMA transfer, the
transfers are suspended. Transfers are also suspended when the DE bit of the CHCR or the
DME bit of the DMAOR are changed to 0.
Figure 9.2 is a flowchart of this procedure.
Rev. 5.00 May 29, 2006 page 265 of 698
REJ09B0146-0500