SH7706 Datasheet, PDF (447/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for
receiving serial data. Serial data reception should be carried out in the following procedure after
setting the SCI in a reception-enabled state.
Start reception
1. Receive error processing and break
Read ORER, PER, and FER
detection: If a receive error occurs,
bits in SCSSR
read the ORER, PER and FER bits
of the SCSSR to identify the error.
PER = 1,
FER = 1,
Yes
or ORER = 1?
After executing the necessary error
processing, clear ORER, PER and
FER all to 0. Receiving cannot
resume if ORER, PER or FER remain
No
set to 1. When a framing error occurs,
the RxD0 pin can be read to detect the
Read the RDRF bit in SCSSR
Error processing break state.
No
RDRF = 1?
Yes
Read reception data of SCRDR
and clear RDRF bit in SCSSR to 0
No
All data received?
2. SCI status check and receive-data read:
Read the SCSSR, check that RDRF is
set to 1, then read receive data from the
SCRDR and clear RDRF to 0. The RXI
interrupt can also be used to determine
if the RDRF bit has changed from 0 to 1.
3. To continue receiving serial data: Clear
RDRF to 0 before the stop bit of the
current frame is received.
Yes
Clear the RE bit in SCSCR to 0
End reception
Figure 14.10 Sample Flowchart for Receiving Serial Data
Rev. 5.00 May 29, 2006 page 399 of 698
REJ09B0146-0500