SH7706 Datasheet, PDF (490/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be known.
• The time-out error (DR) can be detected in receiving.
Module data bus
Internal
data bus
SCFRDR2
(16 stages)
SCFTDR2
(16 stages)
RxD2
SCRSR2
SCTSR2
TxD2
SCK2
RTS2
CTS2
Parity generation
Parity check
Legend:
SCRSR2: Receive shift register 2
SCFRDR2: Receive FIFO data register 2
SCTSR2: Transmit shift register 2
SCFTDR2: Transmit FIFO data register 2
SCSMR2: Serial mode register 2
SCSCR2: Serial control register 2
SCPCR
SCPDR
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
SCBRR2
Baud rate
generator
Clock
External clock
SCIF
Pφ
Pφ/4
Pφ/16
Pφ/64
TEI
TXI
RXI
BVRI
SCSSR2: Serial status register 2
SCBRR2: Bit rate register 2
SCFCR2: FIFO control register 2
SCFDR2: Number of FIFO data register 2
SCPDR: Port SC data register
SCPCR: Port SC control register
Figure 16.1 SCIF Block Diagram
Rev. 5.00 May 29, 2006 page 442 of 698
REJ09B0146-0500