SH7706 Datasheet, PDF (195/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.9 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Channels A and B are used in two independent channels condition or under the sequential
condition.
2. A break is set before or after instruction execution.
3. A break is set by the number of execution times.
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable the ASID check.
The break control register (BRCR) is a 32-bit read/write register that has break conditions match
flags and bits for setting a variety of break conditions.
Bit
Bit Name
31 to 22 —
21
BASMA
20
BASMB
19 to 16 —
Initial Value R/W
All 0
R
0
R/W
0
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Break ASID Mask A
Specifies whether the bits of the channel A break
ASID7 to ASID0 (BASA7 to BASA0) set in
BASRA are masked or not.
0: All BASRA bits are included in break
condition, ASID is checked
1: No BASRA bits are included in break
condition, ASID is not checked
Break ASID Mask B
Specifies whether the bits of channel B break
ASID7 to ASID0 (BASB7 to BASB0) set in
BASRB are masked or not.
0: All BASRB bits are included in break
condition, ASID is checked
1: No BASRB bits are included in break
condition, ASID is not checked
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 5.00 May 29, 2006 page 147 of 698
REJ09B0146-0500