SH7706 Datasheet, PDF (238/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
8.4.6 PCMCIA Control Register (PCR)
The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the timing for the
assertion or negation of the OE and WE signals for the PCMCIA interface connected to areas 5
and 6. The width for assertion of the OE and WE signals is set by the wait control bit in the WCR2
register.
Bit*
Bit Name
15
A6W3
14
A5W3
13, 12 —
11
A5TED2
7
A5TED1
6
A5TED0
Initial Value R/W
0
R/W
0
R/W
All 0
R
0
R/W
0
R/W
0
R/W
Description
Area 6 Wait Control
The A6W3 bit specifies the number of inserted
wait states for area 6 combined with bits A6W2 to
A6W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0
when area 6 is not set to PCMCIA.
Refer to table 8.10 for details.
Area 5 Wait Control
The A5W3 bit specifies the number of inserted
wait states for area 5 combined with bits A5W2 to
A5W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0
when area 5 is not set to PCMCIA.
The relationship between the setting value and the
number of waits is the same as A6W3.
Reserved
These bits are always read as 0. The write value
should always be 0.
Area 5 Address OE/WE Assert Delay
The A5TED bits specify the address to OE/WE
assert delay time for the PCMCIA interface
connected to area 5.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
Rev. 5.00 May 29, 2006 page 190 of 698
REJ09B0146-0500