SH7706 Datasheet, PDF (43/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 645
Synchronous DRAM Self-Refresh Cycle (TPC = 0) ........................................... 645
Synchronous DRAM Mode Register Write Cycle ............................................... 646
PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 647
PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ... 648
PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) ......... 649
PCMCIA Memory Bus Cycle
(Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3)............................ 650
PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) ..................................... 651
PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ........... 652
PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing) ................ 653
TCLK Input Timing............................................................................................. 655
TCLK Clock Input Timing .................................................................................. 655
Oscillation Settling Time at RTC Crystal Oscillator Power-on ........................... 655
SCK Input Clock Timing ..................................................................................... 655
SCI I/O Timing in Clock Synchronous Mode...................................................... 656
I/O Port Timing.................................................................................................... 656
DREQ Input Timing ............................................................................................ 657
DRAK Output Timing ......................................................................................... 657
TCK Input Timing ............................................................................................... 658
TRST Input Timing (Reset Hold) ........................................................................ 659
H-UDI Data Transfer Timing .............................................................................. 659
ASEMD0 Input Timing ....................................................................................... 659
AUD Timing ........................................................................................................ 660
External Trigger Input Timing............................................................................. 661
A/D Conversion Timing ...................................................................................... 661
Output Load Circuit ............................................................................................. 662
Load Capacitance vs. Delay Time ....................................................................... 663
Appendix
Figure D.1
Figure D.2
Package Dimensions (FP-176C) .......................................................................... 693
Package Dimensions (TBP-208A) ....................................................................... 694
Rev. 5.00 May 29, 2006 page xliii of xlviii