SH7706 Datasheet, PDF (154/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
Virtual address
31
12 11
4 3 210
MMU
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
0 V U Tag address
1
LW0 LW1 LW2 LW3
255
Physical address
Legend:
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
CMP0 CMP1 CMP2 CMP3
Hit signal 1
Figure 5.2 Cache Search Scheme (Normal Mode)
5.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is shown in
table 5.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the
miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU
in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0
and the V bit is set to 1.
Rev. 5.00 May 29, 2006 page 106 of 698
REJ09B0146-0500