SH7706 Datasheet, PDF (35/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Figures
Section 1 Overview
Figure 1.1 SH7706 Block Diagram....................................................................................... 3
Figure 1.2 Pin Assignment (FP-176C) .................................................................................. 4
Figure 1.3 Pin Assignment (TBP-208A) ............................................................................... 5
Section 2 CPU
Figure 2.1 Register Configuration......................................................................................... 14
Figure 2.2 General Registers ................................................................................................. 15
Figure 2.3 System Registers.................................................................................................. 16
Figure 2.4 Control Registers ................................................................................................. 17
Figure 2.5 Data Format in Memory....................................................................................... 21
Figure 2.6 Processor State Transitions .................................................................................. 50
Section 3 Memory Management Unit (MMU)
Figure 3.1 MMU Functions................................................................................................... 52
Figure 3.2 Virtual Address Space Mapping .......................................................................... 54
Figure 3.3 Overall Configuration of the TLB ....................................................................... 60
Figure 3.4 Virtual Address and TLB Structure ..................................................................... 61
Figure 3.5 TLB Indexing (IX = 1)......................................................................................... 62
Figure 3.6 TLB Indexing (IX = 0)......................................................................................... 63
Figure 3.7 Objects of Address Comparison .......................................................................... 64
Figure 3.8 Operation of LDTLB Instruction ......................................................................... 67
Figure 3.9 Synonym Problem................................................................................................ 69
Figure 3.10 MMU Exception Generation Flowchart............................................................... 74
Figure 3.11 MMU Exception Signals in Instruction Fetch ..................................................... 75
Figure 3.12 MMU Exception Signals in Data Access............................................................. 76
Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access........................ 78
Section 4 Exception Processing
Figure 4.1 Vector Addresses ................................................................................................. 82
Figure 4.2 Example of Acceptance Order of General Exceptions......................................... 84
Section 5 Cache
Figure 5.1 Cache Structure.................................................................................................... 99
Figure 5.2 Cache Search Scheme (Normal Mode) ................................................................ 106
Figure 5.3 Write-Back Buffer Configuration ........................................................................ 107
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access ..................... 110
Rev. 5.00 May 29, 2006 page xxxv of xlviii