SH7706 Datasheet, PDF (75/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
2.3.3 Instruction Formats
Table 2.3 explains the meaning of instruction formats and source and destination operands. The
meaning of the operands depends on the operation code. The following symbols are used.
xxxx: Operation code
mmmm: Source register
nnnn: Destination register
iiii:
Immediate data
dddd: Displacement
Table 2.3 Instruction Formats
Instruction Format
0 format 15
xxxx xxxx
Source
Operand
0—
xxxx xxxx
Destination
Operand
—
Instruction
Example
NOP
n format
m
format
15
xxxx nnnn xxxx
15
xxxx mmmm xxxx
0—
xxxx
Control register or
system register
Control register or
system register
0 mmmm: register
xxxx direct
mmmm: register
indirect with post-
increment
mmmm: register
indirect
mmmm: PC-
relative using Rm
nnnn: register
direct
nnnn: register
direct
nnnn: register
indirect with
pre-decrement
Control register
or system
register
Control register
or system
register
—
—
MOVT
Rn
STS
MACH,Rn
STC.L
SR,@–Rn
LDC
Rm,SR
LDC.L
@Rm+,SR
JMP
@Rm
BRAF
Rm
Rev. 5.00 May 29, 2006 page 27 of 698
REJ09B0146-0500