SH7706 Datasheet, PDF (26/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

6.6 Interrupt Response Time................................................................................................... 135
Section 7 User Break Controller ..................................................................................... 139
7.1 Feature .............................................................................................................................. 139
7.2 Register Description.......................................................................................................... 141
7.2.1 Break Address Register A (BARA) ..................................................................... 141
7.2.2 Break Address Mask Register A (BAMRA)........................................................ 142
7.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 142
7.2.4 Break Address Register B (BARB)...................................................................... 144
7.2.5 Break Address Mask Register B (BAMRB) ........................................................ 144
7.2.6 Break Data Register B (BDRB) ........................................................................... 144
7.2.7 Break Data Mask Register B (BDMRB).............................................................. 145
7.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 145
7.2.9 Break Control Register (BRCR) .......................................................................... 147
7.2.10 Execution Times Break Register (BETR)............................................................ 150
7.2.11 Branch Source Register (BRSR).......................................................................... 151
7.2.12 Branch Destination Register (BRDR) .................................................................. 152
7.2.13 Break ASID Register A (BASRA)....................................................................... 152
7.2.14 Break ASID Register B (BASRB) ....................................................................... 153
7.3 Operation .......................................................................................................................... 153
7.3.1 Flow of the User Break Operation ....................................................................... 153
7.3.2 Break on Instruction Fetch Cycle......................................................................... 154
7.3.3 Break by Data Access Cycle................................................................................ 154
7.3.4 Sequential Break .................................................................................................. 155
7.3.5 Value of Saved Program Counter ........................................................................ 155
7.3.6 PC Trace .............................................................................................................. 156
7.3.7 Usage Examples................................................................................................... 158
7.4 Usage Note........................................................................................................................ 162
Section 8 Bus State Controller (BSC) ........................................................................... 163
8.1 Feature .............................................................................................................................. 163
8.2 Input/Output Pin................................................................................................................ 165
8.3 Area Overview .................................................................................................................. 166
8.3.1 PCMCIA Support ................................................................................................ 170
8.4 Register Description.......................................................................................................... 173
8.4.1 Bus Control Register 1 (BCR1) ........................................................................... 174
8.4.2 Bus Control Register 2 (BCR2) ........................................................................... 177
8.4.3 Wait State Control Register 1 (WCR1)................................................................ 179
8.4.4 Wait State Control Register 2 (WCR2)................................................................ 182
8.4.5 Individual Memory Control Register (MCR)....................................................... 186
8.4.6 PCMCIA Control Register (PCR)........................................................................ 190
Rev. 5.00 May 29, 2006 page xxvi of xlviii