SH7706 Datasheet, PDF (127/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.6.3 Usage Examples
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's
V bit. R0 specifies the write data and R1 specifies the address.
; R0=H'1547 381C R1=H'F201 3000
; MMUCR.IX=0
; VPN(31–17)=B'000 1010 1010 0011 VPN(11–10)=B'10 ASID=B'0001 1100
; corresponding entry association is made from the entry selected by
; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to
; 0,achieving invalidation.
MOV.L R0,@R1
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB
entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address
and the data section of a selected entry is read to R1.
; R0=H'F300 4300
; MOV.L @R0,R1
VPN(16-12)=B'0 0100
Way 3
3.7 Usage Note
3.7.1 Use of Instructions Manipulating MD and BL Bits in SR
Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC
@Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB
instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or
P2 space).
Rev. 5.00 May 29, 2006 page 79 of 698
REJ09B0146-0500