SH7706 Datasheet, PDF (17/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
14.3.8 SC Port
Control Register
(SCPCR)
16.1 Feature
Figure 16.1 SCIF
Block Diagram
Page
381
442
Revision (See Manual for Details)
Table amended
Bit
Bit Name Initial Value R/W
11
SCP5MD1 1
R/W
10
SCP5MD0 0
R/W
9
SCP4MD1 1
R/W
8
SCP4MD0 0
R/W
7
SCP3MD1 1
R/W
6
SCP3MD0 0
R/W
5
SCP2MD1 0
R/W
4
SCP2MD0 0
R/W
Description
See section 17.1.10, SC Port Control Register
(SCPCR).
Figure amended
RxD2
TxD2
SCK2
RTS2
CTS2
SCFRDR2
(16 stages)
SCRSR2
SCFTDR2
(16 stages)
SCTSR2
Parity generation
Parity check
SCPCR
SCPDR
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
Ex
16.3.6 Serial Control 451
Register 2 (SCSCR2)
16.4.1 Serial
479
Operation
Serial data reception:
Bit table amended
Initial
Bit Bit Name Value R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
Description
00: Internal clock, SCK pin used for I/O pin (input signal is
ignored)
01: Internal clock, SCK2 pin used for clock output^*1
10: External clock, SCK2 pin used for clock input^*2
11: External clock, SCK2 pin used for clock input^*2
Notes: 1. The output clock frequency is 16 times the bit
rate.
2. The input clock frequency is 16 times the bit rate.
Description amended
5. When modem control is enabled, the RTS2 signal is output
when SCFRDR2 is full. ...
Rev. 5.00 May 29, 2006 page xvii of xlviii