SH7706 Datasheet, PDF (514/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9 FIFO Control Register 2 (SCFCR2)
The FIFO control register 2 (SCFCR2) resets the number of data in the SCFTDR2 and SCFRDR2,
sets the number of trigger data, and contains an enable bit for the loop back test. The SCFCR2 is
always read and written by the CPU.
Initial
Bit Bit Name Value R/W Description
7
RTRG1 0
R/W Trigger of the Number of Receive FIFO Data
6
RTRG0 0
R/W Set the reference number of the receive data full.
The RDF in SCSSR2 is set to 1, when the receiving data
count has exceeded the following trigger number.
Trigger number of receive data.
00:
1
01:
4
10:
8
11:
14
5
TTRG1
0
R/W Trigger of the Number of Transmit FIFO Data
4
TTRG0
0
R/W Set the reference number of the send data empty. The
TDFE in SCSSR2 is set to 1, when the transmitting data
count has fallen the following trigger number.
Trigger number of transmit data.
00:
8 (8)
01:
4 (12)
10:
2 (14)
11:
1 (15)
Note: Values in brackets mean the number of empty bytes
in SCFTDR when the TDFE is set.
3
MCE
0
R/W Modem Control Enable
Enables the modem control signals CTS2 and RTS2.
0: Disables the modem signal*
1: Enables the modem signal
Note: * The CTS2 is fixed to active 0 regardless of the
input value, and the RTS2 is also fixed to 0.
Rev. 5.00 May 29, 2006 page 466 of 698
REJ09B0146-0500