SH7706 Datasheet, PDF(46/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (46/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Table 10.3 Available Combination of Clock Mode and FRQCR Values................................. 308

Section 12 Timer Unit (TMU)

Table 12.1 Pin Configuration ................................................................................................... 325

Table 12.2 TMU Interrupt Sources .......................................................................................... 338

Section 13 Realtime Clock (RTC)

Table 13.1 RTC Pin Configuration .......................................................................................... 341

Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values) ................... 360

Section 14 Serial Communication Interface (SCI)

Table 14.1 SCI Pins 367

Table 14.2 SCSMR Settings..................................................................................................... 383

Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode ........................................ 384

Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................ 387

Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................ 388

Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. 389

Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)..... 389

Table 14.8 Serial Mode Register Settings and SCI Communication Formats.......................... 391

Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................ 391

Table 14.10 Serial Communication Formats (Asynchronous Mode) ......................................... 393

Table 14.11 Receive Error Conditions and SCI Operation ........................................................ 401

Table 14.12 SCI Interrupt Sources ............................................................................................. 417

Table 14.13 SCSSR Status Flags and Transfer of Receive Data................................................ 418

Section 15 Smart Card Interface

Table 15.1 Pin Configuration ................................................................................................... 423

Table 15.2 Register Settings for the Smart Card Interface....................................................... 429

Table 15.3 Relationship of n to CKS1 and CKS0 .................................................................... 431

Table 15.4 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0).................................. 431

Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0).................................. 432

Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ...................... 432

Table 15.7 Register Set Values and SCKÏ Pin......................................................................... 433

Table 15.8 Smart Card Mode Operating State and Interrupt Sources ...................................... 437

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1 SCIF Pins................................................................................................................ 445

Table 16.2 SCSMR2 Settings................................................................................................... 460

Table 16.3 Bit Rates and SCBRR2 Settings............................................................................. 461

Rev. 5.00 May 29, 2006 page xlvi of xlviii

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