SH7706 Datasheet, PDF (464/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure
14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously.
Simultaneous transmission and reception of serial data should be carried out in the following
procedure after setting the SCI in a transmission/reception-enabled state.
Start transmission/reception
Read TDRE bit in SCSSR
No
TDRE = 1?
1. SCI status check and transmit data write: Read the
SCSSR, check that the TDRE bit is 1, then write
transmit data in the SCTDR and clear TDRE to
0. The TXI interrupt can also be used to determine
if the TDRE bit has changed from 0 to 1.
Yes
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
Read ORER bit in SCSSR
2. Receive error processing: If a receive error occurs,
read the ORER bit in SCSSR to identify the error.
After executing the necessary error processing,
clear ORER to 0. Transmitting/receiving cannot
resume if ORER remains set to 1.
ORER = 1?
No
3. SCI status check and receive data read: Read the
Yes
SCSSR, check that RDRF is set to 1, then read
receive data from the SCRDR and clear RDRF
to 0. The RXI interrupt can also be used to
Error processing determine if the RDRF bit has changed from 0 to 1.
Read RDRF bit in SCSSR
No
RDRF = 1?
Yes
Read receive data of SCRDR
and clear RDRF bit in SCSSR to 0
No
All data
transmitted/received?
4. To continue transmitting and receiving serial data:
Read the RDRF bit and SCRDR, and clear RDRF
to 0 before the frame MSB (bit 7) of the current
frame is received. Also read the TDRE bit to check
whether it is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0 before the
MSB (bit 7) of the current frame is transmitted.
Note: In switching from transmitting or receiving t
o simultaneous transmitting and receiving,
clear both TE and RE to 0, then set both TE
and RE to 1.
Yes
Clear TE and RE bits
in SCSCR to 0
End transmission/reception
Figure 14.23 Sample Flowchart for Serial Data Transmitting/Receiving
Rev. 5.00 May 29, 2006 page 416 of 698
REJ09B0146-0500