SH7706 Datasheet, PDF (74/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Addressing
Mode
PC-relative
Instruction
Format Effective Address Calculation Method
Rn
Effective address is sum of register PC and
Rn contents.
Calculation Formula
PC + Rn
PC
+
PC + R0
R0
Immediate #imm:8
8-bit immediate data imm of TST, AND, OR, —
or XOR instruction is zero-extended.
#imm:8 8-bit immediate data imm of MOV, ADD,
—
or CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA
—
instruction is zero-extended and multiplied
by 4.
Note:
For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
Rev. 5.00 May 29, 2006 page 26 of 698
REJ09B0146-0500