SH7706 Datasheet, PDF (20/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
24.3.6 Synchronous
DRAM Timing
Figure 24.39
Synchronous DRAM
Mode Register Write
Cycle
Page
646
24.3.7 PCMCIA
652
Timing
Figure 24.45
PCMCIA I/O Bus Cycle
(TED = 2, TEH = 1,
One Wait, External
Wait)
24.3.12 Delay Time 663
Variation Due to Load
Capacitance
Figure 24.63 Load
Capacitance vs. Delay
Time
Revision (See Manual for Details)
Figure amended and note added
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4
CKIO
t_AD
t_AD
t_AD
A11 (A10)*
t_AD
t_AD
A12 (A11)*
A10 to A2
(A9 to A1)*
t_CSD3
t_AD
t_AD
t_AD
t_AD
t_AD
t_AD
t_CSD3
Note: * Items in parentheses ( ) apply to 16-bit bus width
connections.
Figure amended
D15 to D0
(read)
ICIOWR
(write)
D15 to D0
(write)
t_WDD1
t_ICWSD
t_RDS1
t_ICWSD
t_WDH4
t_WDH1
Figure amended
+3
50 pF stipulated
+2
30 pF stipulated
+1
+0
+0
+10
+20
+30
+40
+50
Load Capacitance [pF]
Rev. 5.00 May 29, 2006 page xx of xlviii