SH7706 Datasheet, PDF (338/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.4.7 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and all channels ending
together. At transfer end, the following conditions are applied except the case where the value set
in the DMATCR reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto request)
When the transfer ending conditions are satisfied, DMAC transfer request acceptance is
suspended. The DMAC stops operating after completing the number of transfers that it has
accepted until the ending conditions are satisfied.
In the cycle-steal mode, the operation is the same regardless of whether the transfer request is
detected by the level or at the edge.
(b) Burst mode, edge detection (external request, internal request, and auto request)
The timing from the point where the ending conditions are satisfied to the point where the
DMAC stops operating differs from that in cycle steal mode. In the edge detection in the burst
mode, though only one transfer request is generated to start up the DMAC, stop request
sampling is performed in the same timing as transfer request sampling in the cycle-steal mode.
As a result, the period when stop request is not sampled is regarded as the period when transfer
request is generated, and after performing the DMA transfer for this period, the DMAC stops
operating.
(c) Burst mode, level detection (external request)
Same as described in (a).
(d) Bus timing when transfers are suspended
The transfer is suspended when one transfer ends. Even if transfer ending conditions are
satisfied during read in the direct address transfer in the dual address mode, the subsequent
write process is executed, and after the transfer in (a) to (c) above has been executed, DMAC
operation suspends.
Rev. 5.00 May 29, 2006 page 290 of 698
REJ09B0146-0500