SH7706 Datasheet, PDF (124/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Figure 3.12 shows the MMU exception signals in the data access mode.
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
ID EX MA WB
ID EX MA
ID EX
MMU exception handler
: Exception source stage
: Stage cancellation for instruction
that has begun execution
Legend:
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
NOP = No operation
Handler transition
WB
processing
MA WB
NOP
NOP
IF ID EX MA WB
Figure 3.12 MMU Exception Signals in Data Access
Rev. 5.00 May 29, 2006 page 76 of 698
REJ09B0146-0500