SH7706 Datasheet, PDF (215/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
H'00000000
H'20000000
H'40000000
P0, U0
H'60000000
H'80000000
P1
H'A0000000
P2
H'C0000000
P3
H'E0000000
P4
Logical address space
Area 0 (CS0)
Internal I/O
Area 2 (CS2)
Area 3 (CS3)
Area 4 (CS4)
Area 5 (CS5)
Area 6 (CS6)
Reserved area
H'00000000
H'04000000
H'08000000
H'0C000000
H'10000000
H'14000000
H'18000000
Physical address space
Note:
For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can
optionally generate a physical address for the logical address. It can be applied when the MMU is
off and when the MMU is on and each physical address for the logical address is equal except for
upper three bits.
See table 8.2, for information on converting logical addresses into user-defined physical
addresses.
Figure 8.2 Corresponding to Logical Address Space and Physical Address Space
Rev. 5.00 May 29, 2006 page 167 of 698
REJ09B0146-0500