SH7706 Datasheet, PDF (149/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
5.2 Register Description
The cache includes the following registers. Refer to section 23, List of Registers, for more details
of the addresses and access sizes.
• Cache control register (CCR)
• Cache control register 2 (CCR2)
5.2.1 Cache Control Register (CCR)
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached.
Bit
Bit Name Initial Value R/W
31 to 4 
All 0
R
3
CF
0
R
2
CB
0
R/W
1
WT
0
R/W
0
CE
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Flash
When 1 is set, the V, U and LRU bits of all cache
entries are cleared to 0 (flush).
This bit is always read as 0. Write-back to external
memory is not performed when the cache is flushed.
Cache Write-back
Indicates the cache's operating mode for area P1.
0: Write-through mode
1: Write-back mode
Write through
Indicates the cache's operating mode for area P0, U0,
and P3.
0: Write-back mode
1: Write-through mode
Cache enable
Indicates whether to use the cache function.
0: Cache not used
1: Cache used
Rev. 5.00 May 29, 2006 page 101 of 698
REJ09B0146-0500