SH7706 Datasheet, PDF (156/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 5 Cache
5.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. To allocate
memory shared by this LSI and the external device to an address area to be cached, invalidate the
entries by operating the memory allocating cache as required. If necessary, for the memory shared
by the CPU and the direct memory access controller in this LSI, invalidation must also be
performed in the same way as described above.
5.4 Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions in the privileged mode. The cache is mapped onto the P4 area in virtual address
space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data
array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size
for the address array and data array, and instruction fetches cannot be performed.
5.4.1 Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array (figure
5.4 (1)).
In the address field, specify the entry address for selecting the entry (bits 11 to 4), W for selecting
the way (bits 13 and 12: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), A for selecting
the associative operation (bit 3), and H'F0 to indicate address array access (bits 31 to 24).
In data field, specify the tag address (bits 31 to 10), LRU bits (bits 9 to 4), U bit (bit 1), and V bit
(bit 0). Upper three bits of the tag address (bits 31 to 29) should always be 0.
The following three operations are enabled for the address array.
Address Array Read: Read the tag address, LRU bits, U bit, and V bit of the entry specified by
the entry address and the way number. When reading, no associative operation is performed
regardless of the value of the associative bit (bit A) specified in the address.
Address Array Write (without associative operation): Write the tag address, LRU bits, U bit,
and V bit specified in the data field to the entry specified by the entry address and the way
number. The associative bit (bit A) should be 0. If data is written to the cache line in which U and
V bits are set to 1, the cache line is written back, and then the tag address, LRU bits, U bit, and V
Rev. 5.00 May 29, 2006 page 108 of 698
REJ09B0146-0500