SH7706 Datasheet, PDF (229/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit
Bit Name Initial Value R/W Description
7
A3IW1
1
R/W Area 3 Intercycle Idle Specification
6
A3IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
3 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
5
A2IW1
1
R/W Area 2 Intercycle Idle Specification
4
A2IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
2 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
3, 2 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
A0IW1
1
R/W Area 0 Intercycle Idle Specification
0
A0IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area
0 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
Rev. 5.00 May 29, 2006 page 181 of 698
REJ09B0146-0500