SH7706 Datasheet, PDF (702/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 24 Electrical Characteristics
24.3.8 Peripheral Module Signal Timing
Table 24.8 Peripheral Module Signal Timing
Module
Item
Symbol Min
Max
TMU, Timer input setup time
t_TCLKS
15
—
RTC
Timer clock input setup time
t
15
—
TCKS
Timer clock Edge specification
t_TCKWH
1.5
—
pulse width _{Both edge specification tTCKWL}
2.5
—
Oscillation settling time
t_ROSC
—
3
SCI
Input clock Asynchronization
t_SCYC
4
—
cycle
Clock synchronization
6
—
Input clock rise time
t
—
1.5
SCKR
Input clock fall time
t_SCKF
—
1.5
Input clock pulse width
t_SCKW
0.4
0.6
Transmission data delay time
t_TXD
—
100
Receive data setup time
(clock synchronization)
t
100
—
RXS
Receive data hold time
(clock synchronization)
t_RXH
100
—
RTS delay time
CTS setup time
(clock synchronization)
t_RTSD
t_CTSS
—
100
100
—
CTS hold time
(clock synchronization)
t
100
—
CTSH
Port
DMAC
Output data delay time
Input data setup time 1
Input data hold time 1
Input data setup time 2
Input data hold time 2
Input data setup time 3
Input data hold time 3
DREQ setup time
DREQ hold time
DRAK delay time
t_PORTD
t
PORTS1
t
PORTH1
t
PORTS2
t_PORTH2
t_PORTS3
t
PORTH3
t
DREQ
t
DREQH
t_DRAKD
—
17
15
—
8
—
tcyc + 15 —
8
—
3 × tcyc + 15 —
8
—
6
—
4
—
—
10
Unit Figure
ns 24.47
24.48
tcyc
s
24.44
tcyc 24.50,
24.51
24.50
tscyc
ns 24.51
ns 24.52
ns 24.53
22.54
Rev. 5.00 May 29, 2006 page 654 of 698
REJ09B0146-0500