SH7706 Datasheet, PDF (261/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

This LSI
A14
A13
A12
A1
CKIO
CKE
CSn
RASx
CASx
RD/WR
D15
D0
DQMLU
DQMLL
Section 8 Bus State Controller (BSC)
64M synchronous DRAM
1M × 16-bit × 4-bank
A13
A12
A11
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
DQ0
DQMU
DQML
Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
Address Multiplexing
Synchronous DRAM can be connected without external multiplexing circuitry in accordance with
the address multiplex specification bits AMX3-AMX0 in MCR. Table 8.17 shows the relationship
between the address multiplex specification bits and the bits output at the address pins.
A25 to A17 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs
longword address specification. Connection should therefore be made in the following order:
connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3.
Table 8.18 shows an example of the connection of address pins when AMX[3:0] = 0100 with 32-
bit bus width.
Rev. 5.00 May 29, 2006 page 213 of 698
REJ09B0146-0500