SH7706 Datasheet, PDF (331/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.5
shows the relationship between request modes and bus modes by DMA transfer category.
Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request
Mode
Bus
Transfer
Usable
Mode Size (bits) Channels
Dual
External device with DACK and
external memory
External B/C
8/16/32/128 0,1
External device with DACK and
memory-mapped external device
External memory and external
memory
External memory and memory-
mapped external device
Memory-mapped external device
and memory-mapped external
device
External memory and on-chip
peripheral module
Memory-mapped external device
and on-chip peripheral module
On-chip peripheral module and
on-chip peripheral module
External
All^*1
All^*1
All^*1
All^*2
All^*2
All^*2
B/C
8/16/32/128 0, 1
B/C
8/16/32/128 0 to 3^*5
B/C
8/16/32/128 0 to 3^*5
B/C
8/16/32/128 0 to 3^*5
B/C^*3 8/16/32^*4
B/C^*3 8/16/32^*4
B/C^*3 8/16/32^*4
0 to 3^*5
0 to 3^*5
0 to 3^*5
Single
External device with DACK and
external memory
External B/C
8/16/32/128 0, 1
External device with DACK and
External B/C
memory-mapped external device
8/16/32/128 0, 1
B: Burst, C: Cycle steal
Notes: 1. External requests, auto requests and on-chip peripheral module requests are all
available. For on-chip peripheral module requests, however, SCIF, and A/D converter
cannot be specified as the transfer request source.
2. External requests, auto requests and on-chip peripheral module requests are all
available. When the SCIF, or A/D converter is also the transfer request source,
however, the transfer destination or transfer source must be the SCIF, or A/D converter,
respectively.
3. If the transfer request source is the SCIF, the cycle-steal mode is only available.
4. The access size permitted when the transfer destination or source is an on-chip
peripheral module register.
5. If the transfer request is an external request, channels 0 and 1 are only available.
6. If the transfer request source is the SDRAM, the transfer size should be set smaller
than the bus width.
Rev. 5.00 May 29, 2006 page 283 of 698
REJ09B0146-0500