SH7706 Datasheet, PDF (379/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 12 Timer Unit (TMU)
Bit Bit Name Initial Value R/W Description
5
UNIE
0
R/W Underflow Interrupt Control
Controls enabling of interrupt generation when the
status flag (UNF) indicating TCNT_2 underflow has
been set to 1.
0: Interrupt due to UNF (TUNI) is not enabled.
1: Interrupt due to UNF (TUNI) is enabled.
4
CKEG1 0
R/W Clock Edge
3
CKEG0 0
R/W These bits select the external clock edge when the
external clock is selected, or when the input capture
function is used.
00: Count/capture register set on rising edge
01: Count/capture register set on falling edge
1X: Count/capture register set on both rising and falling
edge
Note: X: Don't care.
2
TPSC2 0
R/W Timer Prescalers
1
TPSC1 0
R/W These bits select the TCNT_2 count clock.
0
TPSC0 0
R/W 000: Internal clock: count on Pφ/4
001: Internal clock: count on Pφ/16
010: Internal clock: count on Pφ/64
011: Internal clock: count on Pφ/256
100: Internal clock: count on clock output of on-chip
RTC (RTCCLK)
101: External clock: count on TCLK pin input
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
12.3.4 Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)
TCOR_0 to TCOR_2 are specified the setting value for TCNT_0 to TCNT_2 when TCNT_0 to
TCNT_2 are underflowed. TMU has 3 timer constant registers, one for each channel.
TCOR_0 to TCOR_2 is a 32-bit read/write register. TCOR is initialized to H'FFFFFFFF by a
power-on reset or manual reset; it is not initialized in standby mode, and retains its contents.
Rev. 5.00 May 29, 2006 page 331 of 698
REJ09B0146-0500